Low Power and High Performance Full Adder in Deep Submicron Technology

The leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. Increasing leakage current in deep-sub micrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This work presents the performance of different full adders in deep-submicron using 45nnm, 65nm and 90nm technology. Finally, the paper explores different circuit techniques to estimate the leakage power consumption has been presented. An illustrative example has been provided to demonstrate the design and simulation of CMOS with various technologies using DSCH and MICROWIND program.